Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
An important step in the manufacture of PLDs is testing the PLDs prior to shipment to a customer. One process for testing a PLD configures the PLD with a test circuit design (also referred to as a test pattern). The test circuit design is configured to test particular resources of the PLD. A test stimulus is applied to the inputs of the test circuit design, and the outputs of the test circuit design are analyzed to capture the resulting state data. The state data is compared with the expected values of the state data to determine whether the test circuit design functioned properly.
Presently, designers generate the expected values for a given test pattern by hand. However, depending on the type of resources being tested, the generation of the expected values by hand may be impractical. For example, the resource under test may be a lookup table (LUT), which can be programmed to implement any one of a multiplicity of different functions (e.g., 65,536 different functions for a LUT having 16 inputs). A LUT may be tested by providing all possible input combinations and testing the output for each input combination. Thus, expected values must be computed for each possible input combination. The problem is further exacerbated if a given test pattern is designed to test multiple LUTS. Accordingly, there exists a need in the art for a method and apparatus that automatically generates expected value data for a circuit design.